Synopsys Jobs

Layout Design, Staff Engineer
Synopsys —Markham, ON
- $106,000–$159,000 a year
- Microsoft Powerpoint
- Microsoft Word
- Computer Science
ASIC Physical Design, Sr Staff Engineer - 16724
Synopsys —Nepean, ON
- $127,000–$191,000 a year
- Microsoft Excel
- In-person
- Communication skills
ASIC Physical Design, Staff Engineer -16723
Synopsys —Nepean, ON
- $106,000–$159,000 a year
- In-person
- Communication skills
Principal ASIC Design Verification Engineer-16988
Synopsys —Nepean, ON
- $146,000–$219,000 a year
- Organizational skills
- In-person
Senior DevOps Engineer
Synopsys —Canada
- $83,000–$124,000 a year
- Azure
- Computer Science
- DevOps
R&D Engineering, Staff Engineer
Synopsys —Canada
- $100,000–$150,000 a year
- Doctoral degree
- Computer Science
- Engineering
ASIC Digital Design, Sr Staff Engineer - 18038
Synopsys —Canada
- $122,000–$183,000 a year
- Microsoft Excel
- Scripting
- Communication skills

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Layout Design, Staff Engineer
Synopsys —Markham, ON
Bachelor’s or Master’s degree in Electrical Engineering or Computer Science or other related field, with 5+ years of relevant experience. What You'll Be Doing.
$106,000–$159,000 a year
ASIC Digital Design, Architect
Synopsys —Markham, ON
Work across design groups and customer support teams to resolve design issues, clarify specifications, and support silicon bring-up. The Impact You Will Have.
$165,000–$248,000 a year
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Layout Design, Staff Engineer

Synopsys -
Markham, ON

Apply Now

Job details

$106,000–$159,000 a year

Qualifications

Microsoft Powerpoint
Microsoft Word
Computer Science
Engineering
Master's degree
Bachelor's
Perl
Scripting
Electrical Engineering
Python

Full job description

We are open to hiring in Ottawa and Toronto (Markham, Mississauga)

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You see layout as engineering, not just drawing boxes. You catch latch-up and EMIR risks early and know how to fix them. You’re comfortable in Custom Compiler SDL or Virtuoso XL, and you close DRC, LVS, Antenna, and DFM issues without drama. You collaborate well with teams around the world, automate what you can, and write down what works so everyone benefits. When someone asks about ESD, you have answers, not just references.

What You'll Be Doing

Creating and optimizing analog mixed signal layouts with a focus on device matching, EMIR awareness, and parasitic minimization using Custom Compiler SDL or Virtuoso XL
Owning top-down macro floor planning and driving layout from concept to sign-off, coordinating with circuit designers and verification teams
Running and resolving DRC, LVS, Antenna, DFM, and other physical verification checks, making layout choices that reduce rework later
Performing PERC verification for ESD and latch-up, proactively identifying and fixing risks before tape out
Use internal AI tools to reduce layout efforts and increase productivity
Collaborating with layout teams in other geographies, sharing best practices, and keeping everyone moving in the same direction
Documenting new methodologies and improvements in MS Word and PowerPoint, making sure the team can repeat and scale what works
Automating layout and verification flows through scripting in partnership with the automation team, enabling engineers to spend more time solving problems and less time on repetitive tasks

What You'll Need

Bachelor’s or Master’s degree in Electrical Engineering or Computer Science or other related field, with 5+ years of relevant experience.
Demonstrated expertise in analog mixed signal layout, with hands-on experience in device and signal matching, EMIR, and parasitic optimization

Proficiency with custom layout tools such as Custom Compiler SDL or Virtuoso XL
Solid command of DRC, LVS, Antenna, DFM, and other physical verification processes
Experience with PERC verification for ESD and latch-up; you know what to look for and how to fix it
Ability to own and floorplan top-down macros, coordinating layout from high-level architecture to final sign-off
Scripting skills in TCL, Perl, or Python to automate tasks and improve flows is a plus
Experience creating clear methodology documentation using MS Word and PowerPoint is a plus

The Impact You Will Have

Deliver layouts that pass verification the first time, cutting down on iteration cycles and speeding up tape out schedules for the whole team
Raise the bar on device matching, EMIR, and parasitic performance, improving silicon yield and reliability for every project you touch
Reduce post-layout surprises by building ESD and latch-up protection into the design, not after the fact
Streamline global team workflows by sharing automation and documentation that actually gets used
Push the quality of the overall design process, leaving a trail of improvements and higher standards for others to build on

Who You Are

You anticipate layout risks and solve them before they become problems in silicon
You collaborate with global teams and can get alignment even when everyone is remote
You write down what works, share it, and make sure it’s repeatable for others
You find ways to automate the drudge work, freeing up time for real engineering
You explain layout tradeoffs clearly, whether in a meeting or in a slide deck
You care about the details, but you don’t lose sight of the bigger project goals

The Team You'll Be Part Of

Your recruiter will share more about the team structure and mission during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the benefits during the hiring process.

#LI-NK4

Apply Now

Refine Your Search

Layout Design, Staff Engineer

ASIC Physical Design, Sr Staff Engineer - 16724

ASIC Physical Design, Staff Engineer -16723

Principal ASIC Design Verification Engineer-16988

Senior DevOps Engineer

R&D Engineering, Staff Engineer

ASIC Digital Design, Sr Staff Engineer - 18038

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