Date posted 05/06/2026
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
You are a visionary and detail-oriented principal engineer, passionate about pushing the boundaries of analog circuit design in high-speed interfaces. With a deep technical foundation and proven leadership skills, you thrive in collaborative environments and are eager to mentor the next generation of engineers. Your expertise in SerDes and analog macros enables you to dissect complex architectural requirements and translate them into robust, scalable designs. You are adept at balancing power, area, and performance trade-offs, and you proactively seek innovative solutions to technical challenges. Your experience spans both the theoretical and practical aspects of circuit design—from transistor-level fundamentals to silicon-proven implementations. You champion rigorous verification methodologies and leverage advanced simulation tools to ensure the highest quality outcomes. As a communicator, you clearly articulate your ideas to peers, customers, and junior team members, fostering a culture of learning and excellence. You are motivated by the opportunity to shape industry-leading IP products that power tomorrow’s technology, and you approach every project with a commitment to reliability, efficiency, and continuous improvement. Your adaptability and curiosity make you a valuable contributor to cross-functional teams, and you are excited to make a lasting impact at Synopsys.
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Own the architecture, design, and implementation of analog macro-level circuits for SerDes IP.
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Track and review the technical progress of sub-block owners, ensuring alignment with project goals.
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Interpret SerDes standards and architecture documents to develop detailed analog specifications.
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Identify and refine circuit implementations, optimizing for power, area, and performance targets.
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Propose and execute design and verification strategies using advanced simulator features for robust outcomes.
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Oversee physical layout to minimize parasitics, device stress, and process variation impacts.
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Collaborate closely with digital RTL engineers on calibration, adaptation, and control algorithms for analog circuits.
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Present simulation data and technical insights for peer and customer reviews.
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Mentor and review the progress of junior engineers, fostering growth and technical excellence.
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Document design features, methodologies, and test plans for internal and customer use.
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Consult on electrical characterization and testing of circuits within the SerDes IP product portfolio.
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Drive innovation and quality in Synopsys’ industry-leading SerDes IP solutions.
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Elevate the performance and reliability of analog designs, enabling next-generation connectivity standards.
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Contribute to the success of global customers by delivering robust, silicon-proven analog macros.
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Enhance cross-functional collaboration across design, layout, and digital teams.
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Mentor and develop junior engineers, strengthening Synopsys’ talent pipeline.
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Influence the direction of advanced analog design methodologies and verification strategies.
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Provide technical leadership in customer engagements and peer reviews.
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Support continuous improvement in design processes and documentation practices.
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PhD with 7+ years, or MSc with 10+ years of SerDes/high-speed analog design experience.
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Expertise in transistor-level circuit design and strong CMOS design fundamentals.
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Silicon-proven experience implementing circuits for TX, RX, and Clock paths within SerDes architectures.
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Leadership experience in guiding small teams through macro-level design projects.
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In-depth knowledge of SerDes sub-circuits such as equalizers, samplers, drivers, serializers, deserializers, VCOs, phase interpolators, DLLs, PLLs, bandgap references, ADCs, and DACs.
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Advanced skills in optimizing FinFET CMOS layouts to minimize parasitics and local device mismatches.
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Awareness of ESD and reliability issues, including circuit techniques and layout strategies.
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Proficiency with EDA tools for schematic entry, physical layout, and design verification.
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Experience with SPICE simulators for detailed circuit analysis.
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Familiarity with analog behavioral modeling and simulation control using Verilog-A.
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Programming experience in TCL, Perl, C, Python, and MATLAB for design automation and data analysis.
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Analytical thinker with exceptional problem-solving skills.
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Collaborative leader and effective communicator.
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Detail-oriented and methodical in approach.
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Adaptable and open to learning new technologies.
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Mentor and role model for junior engineers.
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Self-motivated and proactive in driving project outcomes.
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Committed to excellence, reliability, and innovation.
You will join a dynamic and multidisciplinary team of analog, digital, and mixed-signal engineers dedicated to developing industry-leading SerDes IP solutions. The team is focused on delivering high-performance, reliable, and scalable designs that enable advanced connectivity in semiconductor products. Collaboration, mentorship, and technical innovation are at the core of the team’s culture, providing an environment where your expertise and leadership will have a direct impact on both product and team success.
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact [email protected].
