ottawa, on senior asic synthesis and sta engineer Jobs – 4 Openings This Week

Senior ASIC Synthesis and STA Engineer
Ciena —Ottawa, ON
- $109,000–$174,000 a year
- Full-time
- Engineering
- Bachelor's
- No university degree
- Employee stock purchase plan
- Dental care
Senior Digital ASIC Design Engineer
Ciena —Ottawa, ON
- $109,000–$174,000 a year
- Full-time
- Computer science
- Computer Science
- Engineering
- Employee stock purchase plan
- Dental care
5d
ASIC Physical Design, Sr Staff Engineer - 16724
Synopsys —Nepean, ON
- $127,000–$191,000 a year
- Microsoft Excel
- In-person
- Communication skills
Digital Design Engineer Prime (FEC)
Ciena —Ottawa, ON
- $133,100–$212,500 a year
- Full-time
- Engineering
- C++
- Bachelor's
- Employee stock purchase plan
- Dental care

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Senior ASIC Synthesis and STA Engineer
Ciena —Ottawa, ON
Collaborate closely with ASIC integration, IP development, physical design, and external Electronic Design Automation (EDA) partners to align frontend and…
$109,000–$174,000 a year
Senior Digital ASIC Design Engineer
Ciena —Ottawa, ON
Education: Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science. Application of digital design concepts including synthesis,…
$109,000–$174,000 a year
5d

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senior asic synthesis and sta engineer jobs near ottawa, on

Senior ASIC Synthesis and STA Engineer

Ciena -
Ottawa, ON

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Job details

Full-time
$109,000–$174,000 a year

Qualifications

Engineering
Schedule management
Bachelor's
Computer Engineering
Scripting
Electrical Engineering
Python
Debugging

Full job description

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.

Ciena’s next-generation Wavelogic Digital Signal Processor (DSP) programs rely on deep technical excellence, cross-functional collaboration, and continuous innovation. This role offers the opportunity to shape the frontend implementation of industryleading ASIC technology and contribute to the methodologies that keep Ciena at the forefront of highperformance optical networking.

How you will make an impact:

Execute frontend implementation for assigned IP subsystems, including synthesis, static timing analysis, logical equivalence checking, and clock domain crossing validation

Develop and maintain timing constraints to support synthesis and signoff for subsystem integration

Perform logical equivalence verification between Register Transfer Level (RTL) and gatelevel netlists throughout pre and postlayout stages

Validate clock domain crossings for toplevel ASIC integration to ensure functional integrity

Create and optimize scripts, tools, and documentation that improve synthesis and static timing workflows

Implement engineering change orders (ECOs) to support iterative design refinement

Collaborate closely with ASIC integration, IP development, physical design, and external Electronic Design Automation (EDA) partners to align frontend and backend implementation activities

The must haves:

B.Sc. in Electrical Engineering, Computer Engineering, or a related discipline (or equivalent experience)

Industry experience using synthesis and/or static timing analysis tools within an ASIC development environment

Knowledge of ASIC implementation flows, including synthesis, timing analysis, logical equivalence checking, and clock domain crossing validation

Familiarity with RTL design principles and hardware description languages

Ability to work effectively within multidisciplinary engineering teams and manage deliverables to project schedules

Nice to haves:

Experience with additional frontend or backend design activities such as floorplanning, Design for Testability (DFT), or place and route

Handson exposure to deepsubmicron ASIC technologies and advanced timing closure methodologies

Scripting experience (e.g., Python, Tcl, or similar) to enhance automation and debug workflows

Background supporting DSPcentric or highspeed ASIC development programs

Experience working with external EDA vendors or foundry technology teams

Pay Range:

The annual salary range for this position is $109,000 - $174,000 CAD.

Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.

Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.

At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.

Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.

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Refine Your Search

senior asic synthesis and sta engineer jobs in ottawa, on

Senior ASIC Synthesis and STA Engineer

Senior Digital ASIC Design Engineer

ASIC Physical Design, Sr Staff Engineer - 16724

Digital Design Engineer Prime (FEC)

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