Date posted 06/02/2026
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You have spent years in the transistor-level trenches, building analog and mixed-signal circuits that have to work at 112Gbps and beyond, not just in simulation but in silicon, in production, in the field. You know the difference between a circuit that looks clean in Hspice and one that survives FinFET parasitics, process corners, and temperature swings. That difference keeps you up at night in a good way.
You think in tradeoffs. Power versus area. Speed versus reliability. Layout proximity effects versus routing congestion. When someone asks for another 5% performance, you already know which knob to turn and what it will cost elsewhere. You have debugged enough silicon to know that the issue is usually something you decided three months ago during floorplanning, and you have learned to catch those decisions earlier.
Working with digital engineers does not intimidate you. You can sit with an RTL team, talk through calibration loops and adaptation algorithms, and walk out with a clear interface spec that actually works. You do not wait for perfect documentation. You ask the right questions, build the model, run the corner cases, and move. At Synopsys, you will design circuits that power the next generation of datacenters, automobiles, and communications networks, and the team will expect you to bring that same rigor and judgment every day.
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Review SerDes standards like PCI-Express, Ethernet, and CPRI to develop sub-block specifications for analog circuits operating at 112Gbps, 128Gbps, 224Gbps, and higher
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Design and optimize transistor-level circuits including receive equalizers, voltage/current-mode drivers, serializers, deserializers, VCOs, phase interpolators, DLLs, PLLs, bandgap references, ADCs, and DACs in the latest FinFET process nodes
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Propose and execute verification strategies using Hspice, Finesim, PrimeSim, or equivalent simulators to validate power, area, and performance targets across process, voltage, and temperature corners
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Oversee physical layout with your layout team to minimize parasitic resistance and capacitance, manage device mismatch, and mitigate proximity effects and stress-induced variation
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Collaborate directly with digital RTL engineers to co-develop calibration, adaptation, and control algorithms that interface with your analog circuits
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Present simulation data, corner analysis, and design tradeoffs in peer reviews and customer-facing technical discussions
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Mentor junior engineers on circuit design fundamentals, layout best practices, and verification methodology, reviewing their work and guiding them through complex design challenges
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Enable SerDes IP products that meet the performance, power, and area requirements of next-generation datacenter, automotive, and communications applications
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Deliver silicon-proven analog circuits that scale to 224Gbps and beyond, directly affecting time-to-market for customers building cutting-edge systems
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Reduce design risk and iteration cycles by catching layout-induced issues, parasitic effects, and reliability concerns before tapeout
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Strengthen the technical foundation of the analog design team by mentoring engineers and establishing design and verification best practices
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Influence product roadmaps and architecture decisions through your deep understanding of circuit-level tradeoffs and SerDes system requirements
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Contribute to IP reuse and design efficiency by documenting design features, test plans, and lessons learned from silicon bring-up
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Support successful customer deployments by consulting on electrical characterization and helping debug issues found during product validation
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MASc or PhD with 3+ years of CMOS analog and mixed-signal circuit design experience, or Bachelor's degree with additional equivalent experience
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Silicon-proven track record implementing circuits for TX, RX, and clock paths within a SerDes, with designs that have taped out and been validated in production
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Deep hands-on experience designing several of the following: receive equalizers, data samplers, voltage/current-mode drivers, serializers, deserializers, VCOs, phase interpolators, DLLs, PLLs, bandgap references, ADCs, DACs
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Demonstrated ability optimizing FinFET CMOS layout to minimize parasitic resistance and capacitance while managing local device mismatch and proximity effects
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Proficiency with Hspice, Finesim, PrimeSim, or similar SPICE simulators, and experience with EDA tools for schematic entry, physical layout, and design verification
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Working knowledge of ESD circuit techniques, layout practices, and design for reliability considerations including electromigration, IR drop, and aging effects
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Experience with scripting and automation using Python, TCL, Perl, C, or MATLAB. Knowledge of digital timing analysis in PrimeTime or Nanotime is a plus
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You can look at a layout and immediately spot the parasitic that will kill your phase noise spec, and you know how to work with the layout engineer to fix it without blowing the area budget
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When a digital engineer asks if the ADC can sample 10% faster, you do not just say yes or no. You explain the power cost, the noise floor impact, and the alternative architectures worth considering, all in a two-minute conversation that moves the project forward
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You have been through enough tapeouts to know that the details matter. You check your own corner files, you verify your testbench setup, and you do not assume the simulation that worked yesterday still works today after someone updated the PDK
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Mentoring junior engineers is not a box you check. You genuinely care about helping them understand why a circuit works, not just that it works, and you make time to review their schematics even when your own schedule is tight
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You are comfortable presenting simulation data to customers and peers who will ask hard questions, and you welcome that scrutiny because it makes the design better
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You do not need someone to tell you what to optimize. You see the tradeoff space, you know where the design is weak, and you go after it
You will join the Silicon IP R&D team focused on developing high-speed SerDes IP for next-generation datacenter, automotive, and communications applications. The team works across the full analog and mixed-signal design stack, collaborating closely with digital RTL engineers, layout specialists, and characterization teams to deliver production-quality IP that customers integrate into their SoCs. Your recruiter will
