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Sr. Staff R&D Engineer, Analog design-17614

Synopsys -
Ottawa, ON

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Job details

$119,000–$178,000 a year

Qualifications

UNIX
Perforce
Scripting
Linux
Electrical Engineering
Python

Full job description

Date posted 05/31/2026

Category Engineering Hire Type Employee Job ID 17614 Base Salary Range $119000-$178000 Remote Eligible No Date Posted 05/31/2026

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have built and supported the infrastructure that makes silicon design possible — the flows, tools, and environments that help design teams move from concept to tape out with greater reliability and efficiency. You understand that strong execution often depends on the quality of the engineering foundation behind the scenes, whether that means improving a DRC deck, streamlining an extraction flow, or resolving environment issues before they slow a program down. Your work helps teams reduce friction, improve predictability, and keep critical design efforts moving forward.

You are comfortable working across Python automation, physical verification debugging, and direct collaboration with design teams to resolve complex back-end analog design flow issues. You can step into ambiguous problems, ask sharp questions, identify root causes, and implement fixes that hold up across the broader flow rather than creating downstream disruption. At Synopsys, you will contribute to developing and debug design flows that support our silicon foundation IP development and help engineering teams work more effectively.

What You'll Be Doing

Develop, debug and maintain analog design flow based on extraction, simulation and EMIR flows and support project specific design environments for analog design circuit development across global foundation IP R&D team
Debug complex design issues spanning physical verification (DRC/LVS), extraction, simulation, and reliability analysis using Synopsys EDA tools like StarRc, ICV, Hspice, and Customsim, CustomCompiler etc.
Build Python, TCL, and shell-based automation to eliminate manual steps and accelerate design cycles
Configure and support IP project environments including Perforce data management and LSF job scheduling
Collaborate directly with design teams to diagnose bottlenecks and deliver solutions that work for them.

The Impact You Will Have

You will reduce cycle time by automating flows that currently require manual intervention
Your debugging work will unblock critical design milestones, keeping tape out schedules on track across global projects
Your automation will eliminate entire categories of errors, improving first-pass success rates for verification runs
You will shape how new EDA tools get adopted with AI features, ensuring there is smooth integration

What You'll Need

MSEE, BSEE degree with an emphasis on VLSI, Microelectronics, or Electronics Engineering
6+ years of hands-on experience in VLSI design, EDA tool development, or design flow engineering
Deep knowledge of integrated analog circuit design fundamentals and the VLSI development lifecycle
Proficiency in Python and scripting languages for automation
Solid Linux/Unix knowledge and comfort working in command-line environments
Experience with physical verification (DRC/LVS), extraction, simulation, or reliability analysis, is a strong plus
Experience with Cadence Virtuoso,, UltraSim, and Synopsys tools like ICV StarRC, CustomCompiler, CustomSim, or Hspice, is a plus

Who You Are

You are a “problem solver” and can take a vague complaint like "the flow is broken" and can identify whether it's a tool version mismatch, a bad configuration, or a fundamental design issue within a short amount of time
You write automation that other engineers can use and modify
You communicate clearly across technical and geographic boundaries
You know when to fix something quickly and when to step back and redesign the approach
You are the kind of engineer that collaborates well with others

The Team You'll Be Part Of

You will be part of the Silicon Design & Verification business, the design enablement team building solutions for designing and verifying advanced silicon chips. This R&D group provides EDA tools, processes, and models support that help customers optimize chips for power, cost, and performance while cutting months off project schedules.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

#LI-DP1

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact [email protected].

Apply Now

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